1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to memory circuits having different local word line driving circuit configurations.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
In semiconductor memory devices, word lines are generally configured to provide address paths for an array of memory cells. In particular, word lines are often arranged orthogonal to bit lines with their intersections arranged at memory cells of an array. In order to access a particular memory cell, address information of the memory cell is applied along a word line coupled thereto and logic information is subsequently applied along a bit line coupled to the memory cell. The word lines used in such a capacity of the memory circuit are referred to herein as local word lines and may alternatively be referenced in the semiconductor industry as sub-word lines in some embodiments. A plurality of local word lines along a dimension of the memory array, such as those associated with a block of the memory array, may be coupled to the same signal propagation line to provide address information to a selected local word line. The signal propagation line common to the plurality of local word lines is referred to herein as a global word line and may be alternatively referenced in the semiconductor industry as a main word line.
Word line driving circuits are coupled to each of the local word lines and are configured to selectively allow and prohibit the propagation of a signal from the global word line to each of the local word lines coupled thereto. More specifically, each of the word line driving circuits are configured to selectively allow and disallow the transfer of a voltage pulse from the global word line to the respective local word line coupled thereto upon selection or deselection of control lines coupled to the local word line driving circuits. Consequently, the word line driving circuits serve as selection devices for the plurality of local word lines. Likewise, the global word line is generally equipped with a global word line driving circuit to allow and disallow the propagation of a signal along the global word line.
In general, the speed at which a particular memory cell may be addressed is dependent on, among other things, the resistance and capacitance values of the global word line circuit, the global word line, the word line driving circuit, and the local word line coupled to the block of memory cells comprising the particular memory cell. The lapse of time to induce signal propagation due to such resistance and capacitance values may generally be referred to as the RC delay of the address path. In conventional memory circuit designs, word line driving circuits for a given memory array have the same size and, thus, have the same associated resistance and capacitance values and resulting drive capability. Capacitance along interconnect lines, such as a global word line and local word lines, however, generally increase along the length of the lines, increasing the time needed to induce a voltage pulse from one end of the line to another. Consequently, the RC delay for an address path of a memory cell increases as its respective local word line and word line driving circuit are positioned farther from the global word line driving circuit. In effect, word line driving circuits positioned closer to the global word line driving circuit along the global word line may be asserted faster than those positioned farther from the global word line driving circuit.
Conventional memory circuit configurations are generally designed to accommodate a predetermined maximum RC delay such that the memory circuits may function in a practical amount of time and with relatively low power consumption. Such design configurations include sizing the global word line circuit, the global word line, the word line driving circuits, and the local word lines. For example, the word line driving circuits are generally sized such that the largest RC delays for the memory circuit (i.e., the RC delays along the address paths of the memory cells coupled to the word line farthest from the global word line driving circuit) are less than the predetermined maximum RC delay. In general, the capacitance of a word line driving circuit is inversely proportional with the size of the word line driving circuit and, as such, the word line driving circuits may be sized sufficiently large to accommodate the increasing capacitance at the end of the global word line. Large driving circuit sizes, however, undesirably occupy valuable die space, limiting the size of the memory array within the memory circuit. In addition, large driving circuits generally require larger operating currents and tend to generate larger standby leakage current, increasing the power consumption of the memory circuit.
Accordingly, it would be advantageous to develop a memory circuit which allows smaller word line driving circuits to be used for a given RC delay, a given number of memory cells coupled thereto, and a given size of a global word line coupled thereto. In addition, it would be beneficial to develop a memory circuit configuration which functions faster and with lower power consumption. Furthermore, it would be desirable to offer a memory circuit configuration which allows greater flexibility for increasing memory array size on a die.